The present invention relates generally to I/O (input/output) interfaces. In particular, the present invention relates to a method and apparatus for controlling a multi-mode I/O interface.
The design of computer hardware components which can function within both the work station markets, as well as the server computer markets, is generally regarded as a desired goal. However, peripheral components which interface with a designed hardware component vary depending on whether the hardware component is functioning within a work station environment or a server environment. Depending on the type of peripheral component, input/output (I/O) communication with the various peripheral components requires the ability to communicate with various interface protocols.
For example, referring to FIGS. 1A and 1B, a memory controller hub (MCH) 110 is depicted as configured within a work station platform (FIG. 1A) or a server platform (FIG. 1B). Referring to FIG. 1A, the memory controller hub 110, within a work station platform 100, can include a front side bus 104 for interfacing with one or more central processing units (CPU) 102 (102A, 102B, . . . 102N). The memory controller hub 110 may also include a Rambus(trademark) channel 120 for interfacing with one or more RAM memories 120 (120A, . . . 120N). The memory controller hub 110 is also coupled to an I/O controller hub (ICH) 130 which can interface with various peripheral components including peripheral component interfaces (PCI) devices, parallel port devices or integrated drive electronics (IDE) components. In addition, the memory controller hub 110 may include one or more graphics ports 124 (124A, . . . , 124N) for coupling to one or more graphics cards 126 (126A, . . . 126N).
Referring to FIG. 1B, a memory controller hub 210 is depicted as configured within a server platform 200. The memory controller hub 210 is configured more or less as configured in the work station platform 200, including a front side bus 204 for coupling to one or more CPUs 202 and including RAM bus channels 220, 222. The difference is that in the server platform, PCI is a vital component, whereas in the work station platform, connections to various graphics devices via graphics cards and graphics ports such as, for example, accelerated graphics ports (AGP), is desired by consumers. Based on the descriptions of the memory controller hubs 110 and 210, as depicted in both the work station platform 100 and a server platform 200, it would appear that designing of a memory controller hub that can function in both work station platforms as well as server platforms would simply require a memory controller hub capable of supporting interface protocols including both AGP protocols as well as interface protocols, such an a parallel-terminated, source-synchronous interface protocol. Unfortunately, the design of a hardware component which is capable of interfacing with various peripheral components and support the various (input/output) I/O protocols which run the peripheral components is complicated by the various types of signaling protocols implemented by the various I/O protocols.
The various I/O protocols which are supported may be either common-clock protocols or source-synchronous protocols. As known to those skilled in the art, source-synchronous I/O protocols refer to protocols wherein the data and the timing information are transported as a group. Also, depending on the protocol, the signaling may be series terminated or parallel terminated. For source-synchronous protocols, the strobe signals can be complimentary, negative edge driven, rising edge driven or single strobe. In addition, the I/O protocol may require transmission at N-times a core clock frequency.
In summary, the computer hardware components designer must analyze various characteristics of each protocol, which the component will support. The designer must consider the relationship of the data transitions to the I/O clock, the relationship of the strobe transitions to the I/O clock and more importantly, to the data transitions. He must determine the strobe patterns that indicate valid data. Finally, the relationship of the output enable of the strobes and data signals, with respect to the first and last transition for a source terminated protocols, must also be considered. In other words, each protocol has differing electrical and logical specifications. The logical behavior of each protocol can be uniquely described by examining the relationship of the data, strobes, and transmission rates to each other.
Previous source-synchronous I/O designs were designed for either a single protocol or a few related protocols. For example, in the case of a source-synchronous design incorporating both accelerated graphics protocols 4xc3x97 (four times transmission frequency) and accelerated graphics protocol 2xc3x97 (two times transmission frequency), the design was implemented by changing the clock frequency and adding arcs to the state machines responsible for serializing outbound data. While this approach was sufficient for AGP design, the control structure required for an I/O interface using two unrelated protocols, such as AGP and a parallel-terminated, source-synchronous interface protocol, becomes more difficult.
Therefore, there remains a need to overcome one or more limitations in the above described existing art.